Ball grid arrays are made by coating a pad grid on the chip package with high temperature solder, (95% Pb/5% Sn). A glass template is provided with a hole grid corresponding to the pad grid. The holes are filled with copper balls coated with high temperature solder, and the high temperature solder is reflowed to join the balls to the pad. Subsequently, the ball grid package is attached to the next level assembly by a lower temperature solder, e.g. 60% Sn/40% Pb. Ball grid arrays require careful and precise control of soldering temperatures. Replacement or repair of packages having ball grid arrays also requires temperature control for package removal. Many hermetic packages have covers that are bonded to the package by sealing glass. The covers are sealed with sealing glasses at 360-450° C. Ball grid arrays for such packages cannot be made in advance, but must be added as the last step in making the package.
Micro-connection systems have been proposed for testing to produce “known-good-die” One proposed micro-connection system has microbumps on a copper clad polyimide substrate which are to be temporarily pressed against the die for testing purposes. A silicone rubber sheet backing the micro bumped polyimide surface transmits the contact pressure to the microbumps. These proposed microbumps are not suitable for permanent connections, or for hermetically sealed packages.
The Controlled Collapse Chip Connection (C4) is a method of flip chip mounting of semiconductor chips. In the C4 process, solder bumps are formed on a semiconductor chip. The solder bumps are used to connect the chip to its package, such as a single chip module (SCM) or multichip module (MCM). In the C4 process, first a glass passivation layer is formed on the chip with vias in the layer for the input/output contacts, I/Os. After DC sputter cleaning of the via holes, a thin circular pad of chromium is evaporated through a mask. The chromium pad covers the via and forms a ring around the via over the passivation layer sealing the via. The DC sputter cleaning assures low contact resistance to the aluminum I/O pad of the chip and good adhesion to the passivation layer. Next a phased chromium and copper layer is evaporated to provide resistance to multiple reflows in the subsequent processing. This is followed by a pure copper layer to form a solderable metal. A thin layer of gold is added as an oxidation protection layer for the copper. A thick deposit (100-125 μm) of high melting solder (97-95% Pb/3-5% Sn) is evaporated through-a mask onto the chip and then heated to about 365° C. in a hydrogen atmosphere to fuse the solder into truncated spheres adhering to the pads. These solder bumps are fused to gold plated or solder coated pads on the interior surface of the chip package. The solder joints in the C4 design must be high enough to compensate for substrate non-planarity. Also because solder surface tension holds up the chip, a sufficient number of pads is required to support the weight of the chip. This is a concern with bulky, low I/O devices such as memory chips or chip carriers, where multiple dummy pads must be added to support the chip. For this reason, among others, the C4 process has been used for connecting semiconductor chips to a first level package, but has not been successful or widely used for connecting a package, which is substantially heavier than a chip to a higher level assembly.